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MC10EP33, MC100EP33 3.3V / 5V ECL B4 Divider
The MC10/100EP33 is an integrated B4 divider. The differential clock inputs. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EP33's in a system. The 100 Series contains temperature compensation.
http://onsemi.com MARKING DIAGRAMS*
8 8 1 SO-8 D SUFFIX CASE 751 HEP33 ALYW 1 1 8 KEP33 ALYW
* 320 ps Propagation Delay * Maximum Frequency > 4 GHz Typical * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V *
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State
8 1 TSSOP-8 DT SUFFIX CASE 948R
8 HP33 ALYW 1
8 KP33 ALYW 1
* * Safety Clamp on Inputs * Q Output Will Default LOW with Inputs Open or at VEE * VBB Output
H = MC10 K = MC100 A = Assembly Location
L = Wafer Lot Y = Year W = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC10EP33D MC10EP33DR2 MC100EP33D MC100EP33DR2 MC10EP33DT MC10EP33DTR2 MC100EP33DT Package SO-8 SO-8 SO-8 SO-8 TSSOP-8 TSSOP-8 TSSOP-8 Shipping 98 Units/Rail 2500 Tape & Reel 98 Units/Rail 2500 Tape & Reel 100 Units/Rail 2500 Tape & Reel 100 Units/Rail 2500 Tape & Reel
MC100EP33DTR2 TSSOP-8
(c) Semiconductor Components Industries, LLC, 2002
1
September, 2002 - Rev. 5
Publication Order Number: MC10EP33/D
MC10EP33, MC100EP33
PIN DESCRIPTION
PIN RESET 1 R CLK 2 B4 CLK 3 6 Q 7 Q 8 VCC CLK*, CLK* Reset* VBB Q, Q VCC VEE FUNCTION ECL Clock Inputs ECL Asynchronous Reset Reference Voltage Output ECL Data Outputs Positive Supply Negative Supply
* Pins will default LOW when left open.
TRUTH TABLE
VBB 4 5 VEE CLK X Z CLK X Z RESET Z L Q L F Q H F
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
Z = LOW to HIGH Transition Z = HIGH to LOW Transition F = Divide by 4 Function
CLK tRR RESET
Q
Figure 2. Timing Diagram
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW NA > 4 kV > 200 V > 2 kV Level 1 UL-94 V-0 @ 0.125 in 91 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
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MC10EP33, MC100EP33
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 8 SOIC 8 SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 TSSOP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 190 130 41 to 44 185 140 41 to 44 265 Units V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current 0.5 Min 18 2165 1365 2090 1365 1790 2.0 1890 Typ 26 2290 1490 Max 34 2415 1615 2415 1690 1990 3.3 150 0.5 Min 18 2230 1430 2155 1430 1855 2.0 1955 25C Typ 26 2355 1555 Max 34 2480 1680 2480 1755 2055 3.3 150 0.5 Min 18 2290 1490 2215 1490 1915 2.0 2015 85C Typ 26 2415 1615 Max 34 2540 1740 2540 1815 2115 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 W to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP33, MC100EP33
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 8) Input HIGH Current Input LOW Current 0.5 Min 18 3865 3065 3790 3065 3490 2.0 3590 Typ 26 3990 3190 Max 34 4115 3315 4115 3390 3690 5.0 150 0.5 Min 18 3930 3130 3855 3130 3555 2.0 3655 25C Typ 26 4055 3255 Max 34 4180 3380 4180 3455 3755 5.0 150 0.5 Min 18 3990 3190 3915 3190 3615 2.0 3715 85C Typ 26 4115 3315 Max 34 4240 3440 4240 3515 3815 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 7. All loading with 50 W to VCC-2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 10) Output LOW Voltage (Note 10) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 11) Input HIGH Current Input LOW Current 0.5 Min 18 -1135 -1935 -1210 -1935 -1510 -1410 Typ 26 -1010 -1810 Max 34 -885 -1685 -885 -1610 -1310 0.0 150 0.5 Min 18 -1070 -1870 -1145 -1870 -1445 -1345 25C Typ 26 -945 -1745 Max 34 -820 -1620 -820 -1545 -1245 0.0 150 0.5 Min 18 -1010 -1810 -1085 -1810 -1385 -1285 85C Typ 26 -885 -1685 Max 34 -760 -1560 -760 -1485 -1185 0.0 150 Unit mA mV mV mV mV mV V mA mA
VEE+2.0
VEE+2.0
VEE+2.0
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 W to VCC-2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP33, MC100EP33
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 13) Output LOW Voltage (Note 13) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 14) Input HIGH Current Input LOW Current 0.5 Min 23 2155 1355 2075 1355 1775 2.0 1875 Typ 28 2280 1480 Max 33 2405 1605 2420 1675 1975 3.3 150 0.5 Min 24 2155 1355 2075 1355 1775 2.0 1875 25C Typ 30 2280 1480 Max 36 2405 1605 2420 1675 1975 3.3 150 0.5 Min 25 2155 1355 2075 1355 1775 2.0 1875 85C Typ 31 2280 1480 Max 37 2405 1605 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 13. All loading with 50 W to VCC-2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 16) Output LOW Voltage (Note 16) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 17) Input HIGH Current Input LOW Current 0.5 Min 23 3855 3055 3775 3055 3475 2.0 3575 Typ 28 3980 3180 Max 33 4105 3305 4120 3375 3675 5.0 150 0.5 Min 24 3855 3055 3775 3055 3475 2.0 3575 25C Typ 30 3980 3180 Max 36 4105 3305 4120 3375 3675 5.0 150 0.5 Min 25 3855 3055 3775 3055 3475 2.0 3575 85C Typ 31 3980 3180 Max 37 4105 3305 4120 3375 3675 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 16. All loading with 50 W to VCC-2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP33, MC100EP33
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 19) Output LOW Voltage (Note 19) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 20) Input HIGH Current Input LOW Current 0.5 Min 23 -1145 -1945 -1225 -1945 -1525 -1425 Typ 28 -1020 -1820 Max 33 -895 -1695 -880 -1625 -1325 0.0 150 0.5 Min 24 -1145 -1945 -1225 -1945 -1525 -1425 25C Typ 30 -1020 -1820 Max 36 -895 -1695 -880 -1625 -1325 0.0 150 0.5 Min 25 -1145 -1945 -1225 -1945 -1525 -1425 85C Typ 31 -1020 -1820 Max 37 -895 -1695 -880 -1625 -1325 0.0 150 Unit mA mV mV mV mV mV V mA mA
VEE+2.0
VEE+2.0
VEE+2.0
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 W to VCC-2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40C Symbol VOPP Characteristic Output Voltage Amplitude (See Figure 3) fin < 4.0 GHz fin < 4.5 GHz Propagation Delay to Output Differential Set/Rest Recovery Minimum Pulse width Cycle-to-Cycle Jitter Input Voltage Swing (Differential) Output Rise/Fall Times (20% - 80%) Q, Q 150 90 RESET CLK/Q RESET/Q 300 370 150 550 Min Typ 700 600 380 420 100 480 0.2 800 170 <1 1200 200 150 100 440 470 300 370 200 550 Max Min 25C Typ 700 600 380 420 100 480 0.2 800 180 <1 1200 250 150 120 440 470 320 400 200 550 Max Min 85C Typ 700 600 400 450 100 480 0.2 800 200 <1 1200 280 460 500 ps ps ps ps mV ps Max Unit mV
tPLH, tPHL tRR tPW tJITTER VPP tr tf
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V.
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MC10EP33, MC100EP33
900 800 VOPP, OUTPUT VOLTAGE (mV) 700 600 500 400 300 200 100 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 fin, INPUT FREQUENCY (MHz)
Figure 3. Input Frequency (fin) versus Output Voltage (VOPP)
Q Driver Device Q 50 W 50 W
D Receiver Device D
V TT V TT = V CC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020
- - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC10EP33, MC100EP33
PACKAGE DIMENSIONS
-X- A
8 5
SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-07 ISSUE AA
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDAARD IS 751-07 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
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MC10EP33, MC100EP33
PACKAGE DIMENSIONS
TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A
8x
K REF 0.10 (0.004)
M
0.15 (0.006) T U
S 2X
TU
S
V
S
L/2
8
5
L
1 PIN 1 IDENT 4
B -U-
0.25 (0.010) M
0.15 (0.006) T U
S
A -V-
F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_
C 0.10 (0.004) -T- SEATING
PLANE
D
-W- G DETAIL E
DIM A B C D F G K L M
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MC10EP33, MC100EP33
Notes
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MC10EP33, MC100EP33
Notes
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MC10EP33, MC100EP33
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MC10EP33/D

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